M2000 Unveils Optimized eFPGA Architecture for DSP Functions
MUNICH, Germany—(BUSINESS WIRE)—March 8, 2005—
M2000, an innovator in intellectual property for
reconfigurable semiconductors, today unveiled a new architecture for
the FlexEOS range of embedded FPGA (eFPGA) macros. The new
architecture, FlexEOS-DSP, has been optimized to maximize the
performance and to minimize silicon utilization when implementing
digital signal processing (DSP) applications. ASIC designers now have
an efficient means to add in-silicon reconfigurability to applications
ranging from image processing to wireless and radar.
The new architecture further expands the innovative,
silicon-proven FlexEOS solution. It combines reprogrammable logic
elements with hard-wired functions that are common in most DSP
functions, such as memory blocks, multipliers, accumulators, adders
and subtractors.
"We believe that the addition of these functions constitutes a
very attractive proposition for designers who need to combine DSP
calculating power with the flexibility of a reprogrammable core," said
Gabriele Pulini, M2000's vice president for marketing. "We have
already seen a high level of interest for FlexEOS products in the
communications sector, and we are convinced that these additions will
be the key for expanding the use of FPGA cores in consumer products
such as home digital devices."
About FlexEOS-DSP
The FlexEOS range of embedded FPGA cores are SRAM based, and can
be dynamically reconfigured to change the functionality of ASIC and
SoC circuits after silicon processing and packaging. FlexEOS macros
are currently characterized and manufactured in 90 nanometer CMOS
technology. The silicon density for logic functions is up to 1,350
LUT's per mm2, and the delay for a LUT plus its interconnect is 0.37
ns.
The optional DSP-dedicated blocks offer a variety of operating
modes: signed/unsigned multiplication, multiply-accumulation,
multiply-addition and multiply-subtraction, together with configurable
rounding and saturation for performance, which is also enhanced with
pipeline registers. The memory blocks can be configured as 4, 8 or 16
bits, and have dual ports, which can be configured independently. For
example, a 96K LUT FlexEOS-DSP macro in 90nm contains 768, 500MHz MACs
and 3.4Mb of memory blocks.
Each macro is delivered with a comprehensive software tool suite
for the compilation of the applications which are to run on the macro.
FlexEOS macros are suitable for a wide range of applications, and can
be supplied for any silicon foundry technology.
Availability and Pricing
M2000's range of generic FlexEOS products is available for
production in 90nm. Evaluation versions of the software are available
from M2000. FlexEOS-DSP macros optimized for DSP functions will be
available in Q2 2005. The comprehensive pricing structure, which can
be tailored to individual requirements, includes a license fee for
each project, and royalties on production chips.
About M2000
M2000 was created in 1996 by three EDA and FPGA veterans. The
founding team has more than 17 years in design of innovative FPGA
architectures, and holds numerous patents in the field of configurable
logic and its applications for electronic system validation. M2000's
current focus is the design and development of state of the art
configurable logic technology for the rapidly growing reconfigurable
SoC (System on a Chip) market. Corporate headquarters are located at:
1 Route de Gisy, Parc Burospace, Hall 1bis, Bievres, (91570) France.
North American headquarters are at: 1095 E. Duane Ave. Suite 203,
Sunnyvale, Calif. 94085. Website: http://www.m2000.com Email:
info@m2000.fr.
Contact:
M2000
Gabriele Pulini, +33 1 69 35 32 50
Gabriele.Pulini@m2000.fr
or
Jim Lochmiller, 541-821-3438 (Public Relations)
lochpr@yahoo.com
